VIRAG TIWARI. Simulation Design Analysis and Implementation of DLL Using Scalable C5 CMOS Process For Clock Generation. International Journal of Research & Technology, [S. l.], v. 5, n. 2, p. 09–16, 2017. Disponível em: https://ijrt.org/j/article/view/369. Acesso em: 13 sep. 2025.