ROHIT SACHAN, PROF. SURESH. S. GAWANDE, PROF. SATYARTH TIWARI. High Speed and Area Efficient Adjoint Matrix using Booth Multiplier for FPGA Implementation . International Journal of Research & Technology, [S. l.], v. 9, n. 3, p. 90–95, 2021. Disponível em: https://ijrt.org/j/article/view/361. Acesso em: 13 sep. 2025.