DEEPAK MISHRA, DR. PAYAL SUHANE. Implementation of IEEE 754 Floating Point Multiplier using Partition Technique and Ling-Enhance Adder . International Journal of Research & Technology, [S. l.], v. 10, n. 3, p. 12–16, 2022. Disponível em: https://ijrt.org/j/article/view/290. Acesso em: 30 aug. 2025.