KOMAL GUPTA, PROF. AMRITA PAHADIA, PROF. SATYARTH TIWARI. Efficient VLSI Architecture for Modulo 2n+1 Multiplier using n-bit Inverted Adder . International Journal of Research & Technology, [S. l.], v. 10, n. 1, p. 15–18, 2022. Disponível em: https://ijrt.org/j/article/view/284. Acesso em: 30 aug. 2025.