RAJESH YADAV, PROF. SATYARTH TIWARI. VLSI Architecture for Matrix Multiplier using Parallel To Parallel Input Multiple Output Technique. International Journal of Research & Technology, [S. l.], v. 12, n. 1, p. 20–24, 2024. Disponível em: https://ijrt.org/j/article/view/237. Acesso em: 24 aug. 2025.