RAHUL SHRIVASTAVA,PROF. S.G. KELARKAR,PROF. N.K. MITTAL. FPGA Implementation of Optimized Decimal Floating Point Multiplier using Binary Integer Decimal Encoding. International Journal of Research & Technology, [S. l.], v. 2, n. 1, p. 1–6, 2014. Disponível em: https://ijrt.org/j/article/view/18. Acesso em: 4 oct. 2025.